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CY7C1010DV33
2-Mbit (256K x 8) Static RAM
Features

Functional Description
The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1010DV33 is available in 36-pin SOJ and 44-pin TSOP II packages with center power and ground (revolutionary) pinout. Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations.
Pin and function compatible with CY7C1010CV33 High speed tAA = 10 ns Low active power ICC = 90 mA at 10 ns Low CMOS standby power ISB2 = 10 mA 2.0V data retention Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-Free 36-pin SOJ and 44-pin TSOP II packages

Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE WE OE
IO0 IO1
ROW DECODER
256K x 8 ARRAY
SENSE AMPS
IO2 IO3 IO4 IO5 IO6
COLUMN DECODER
POWER DOWN
IO7
A12 A13 A14
A15
A16
Cypress Semiconductor Corporation Document Number: 001-00062 Rev. *B
*
198 Champion Court
A17
A11
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 6, 2008
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CY7C1010DV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 90 10 Unit ns mA mA
Pin Configuration
Figure 1. 36-Pin SOJ [1] Figure 2. 44-Pin TSOP II [1]
NC NC A4 A3 A2 A1 A0 CE IO0 IO1 VCC VSS IO2 IO3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE IO7 IO6 VSS VCC IO5 IO4 A9 A10 A11 A12 NC NC NC NC
A4 A3 A2 A1 A0 CE IO0 IO1 VCC GND IO2 IO3 WE A17 A16 A15 A14 A13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
NC A5 A6 A7 A8 OE IO7 IO6 GND VCC IO5 IO4 A9 A10 A11 A12 NC NC
Note: 1. NC pins are not connected on the die.
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND [2] ....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State [2] ................................... -0.3V to VCC + 0.3V DC Input Voltage [2] ............................... -0.3V to VCC + 0.3V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage.................................................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
Electrical Characteristics
Over the Operating Range Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 VCC = Min.; IOH = -4.0 mA VCC = Min.; IOL = 8.0 mA 2.0 -0.3 -1 -1 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 10 mA mA -10 Max Unit V V V V A A mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V SOJ 8 8 TSOP II 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board SOJ 59.17 32.63 TSOP II 50.66 17.77 Unit C/W C/W
Note 2. VIL (min.) = -2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns.
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Figure 3. AC Test Loads and Waveforms[3]
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High-Z characteristics: 3.3V OUTPUT 5 pF 1.5V 3.0V ALL INPUT PULSES 90% 10% 90% 10%
30 pF*
GND
(a)
R 317
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
R2 351
Note 3. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
AC Switching Characteristics
Over the Operating Range [4] -10 Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[8, 9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[7] High-Z[6, 7] 10 7 7 0 0 7 5 0 3 5 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE HIGH to High-Z[6, 7] 3 5 0 10 High-Z[6, 7] CE LOW to Low-Z[7] CE LOW to Power-up CE HIGH to Power-down 0 5 3 10 5 100 10 10 s ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Data Retention Characteristics
Over the Operating Range [10] Parameter VDR ICCDR tCDR [11] tR
[ 12]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions
Min 2
Max
Unit V
VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC
10
mA ns ns
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V tCDR
VDR > 2V
3.0V tR
Switching Waveforms
Figure 4. Read Cycle No. 1 [13, 14]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes 10. No inputs may exceed VCC + 0.3V 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 13. The device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle.
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Switching Waveforms
(continued) Figure 5. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Notes 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Switching Waveforms
(continued) Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [17]
tWC
ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H L L L OE X L X H WE X H L H IO0-IO7 High-Z Data Out Data In High-Z IO8-IO15 High-Z Data Out Data In High-Z Power Down Read All Bits Write All Bits Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1010DV33-10VXI CY7C1010DV33-10ZSXI Package Diagram 51-85090 51-85087 Package Type 36-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP II (Pb-Free) Operating Range Industrial
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Package Diagrams
Figure 8. 36-Pin (400-Mil) Molded SOJ (51-85090)
5 1-85 090 -*C
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Package Diagrams
(continued) Figure 9. 44-Pin TSOP II (51-85087)
51-85087-*A
Document Number: 001-00062 Rev. *B
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CY7C1010DV33
Document History Page
Document Title: CY7C1010DV33, 2-Mbit (256K x 8) Static RAM Document Number: 001-00062 REV. ** *A ECN NO. Submission Date 342195 459073 See ECN See ECN Orig. of Change PCI NXR New Data sheet Converted Preliminary to Final. Removed Commercial Operating Range from product offering. Removed -8 ns and -12 speed bin Removed the Pin definitions table. Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed ICC max from 65 mA to 90 mA Changed the description of IIX from "Input Load Current" to "Input Leakage Current" Updated the Thermal Resistance table. Updated footnote #7 on High-Z parameter measurement Added footnote #12 Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. Description of Change
*B
2602853
11/07/08
VKN/PYRS Added 36-pin SOJ package and its related information
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(c) Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-00062 Rev. *B
Revised November 6, 2008
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